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 LIBRARY ieee;
 USE ieee.std_logic_1164.all;
 USE  IEEE.STD_LOGIC_ARITH.all;
 USE  IEEE.STD_LOGIC_UNSIGNED.all;
 ----------------------------------------------------------
 ENTITY vga_monitor IS
 GENERIC (
				 Ha: INTEGER := 96; --Hpulse
				 Hb: INTEGER := 144; --Hpulse+HBP
				 Hc: INTEGER := 784; --Hpulse+HBP+Hactive
				 Hd: INTEGER := 800; --Hpulse+HBP+Hactive+HFP
				 Va: INTEGER := 2; --Vpulse
				 Vb: INTEGER := 35; --Vpulse+VBP
				 Vc: INTEGER := 515; --Vpulse+VBP+Vactive
				 Vd: INTEGER := 525); --Vpulse+VBP+Vactive+VFP
 PORT (   clk: IN STD_LOGIC; --100MHz in our board
			 Hsync, Vsync: BUFFER STD_LOGIC;
			 R, G, B: OUT STD_LOGIC;
			 nblanck, nsync : OUT STD_LOGIC);
 END vga_monitor;
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 ARCHITECTURE Behavioral OF vga_monitor IS
 SIGNAL Hactive, Vactive, dena: STD_LOGIC;
 signal pixel_clk,pixel_clk_1: STD_LOGIC;
 signal Hcount: INTEGER RANGE 0 TO Hd;
 signal Vcount: INTEGER RANGE 0 TO Vd;
 signal clk_counter : std_logic_vector(1 downto 0);
 BEGIN
 -------------------------------------------------------
--Part 1: CONTROL GENERATOR
 -------------------------------------------------------
--Static signals for DACs:
 nblanck <= '1'; --no direct blanking
 nsync <= '0'; --no sync on green
 --Create pixel clock (100MHz->25MHz):
 PROCESS (clk)
 BEGIN
	 IF (clk'EVENT AND clk='1') THEN
		clk_counter <= clk_counter+1;
	 END IF;
 END PROCESS;
 pixel_clk <= clk_counter(1);--25 MHz

 --Horizontal signals generation:
 PROCESS (pixel_clk)
-- VARIABLE Hcount: INTEGER RANGE 0 TO Hd;
 BEGIN
 IF (pixel_clk'EVENT AND pixel_clk='1') THEN
	Hcount <= Hcount + 1;
	 IF (Hcount=Ha) THEN
		Hsync <= '1';
	 ELSIF (Hcount=Hb) THEN
		Hactive <= '1';
	 ELSIF (Hcount=Hc) THEN
		Hactive <= '0';
	 ELSIF (Hcount=Hd) THEN
	   Hsync <= '0';
	   Hcount <= 0;
	 END IF;
 END IF;
 END PROCESS;
 --Vertical signals generation:
PROCESS (Hsync)
BEGIN
	 IF (Hsync'EVENT AND Hsync='0') THEN
	 Vcount <= Vcount + 1;
		 IF (Vcount=Va) THEN
			Vsync <= '1';
		 ELSIF (Vcount=Vb) THEN
			Vactive <= '1';
		 ELSIF (Vcount=Vc) THEN
			Vactive <= '0';
		 ELSIF (Vcount=Vd) THEN
			Vsync <= '0';
			Vcount <= 0;
		 END IF;
	 END IF;
 END PROCESS;
 ---Display enable generation:
 dena <= Hactive AND Vactive;
 
 --Part 2: IMAGE GENERATOR
 -------------------------------------------------------
 PROCESS (Hsync, Vsync, Vactive, dena)
 VARIABLE line_counter: INTEGER RANGE 0 TO Vc;
 BEGIN
 IF (Vsync='0') THEN
 line_counter := 0;
 ELSIF (Hsync'EVENT AND Hsync='1') THEN
	 IF (Vactive='1') THEN
	-- line_counter := line_counter + 1;
	 END IF;
 END IF;
 IF (dena='1') THEN
		 IF (HCount>144 and HCount<464 and Vcount > 35 and Vcount < 275) THEN
		 R <= '1';
		 G <= '0';
		 B <= '0';
		 ELSE
		 R <= '1';
		 G <= '0';
		 B <= '0';
		 END IF;
 ELSE
		 R <= '0';
		 G <= '0';
		 B <= '0';
 END IF;
END PROCESS;
END Behavioral;